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| SI5100 SiPHYTM OC-48/STM-16 SONET/SDH TRANSCEIVER Features Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX Data rates supported: SONET-compliant loop timed OC-48/STM-16 through 2.7 Gbps operation FEC Programmable slicing level and sample phase adjustment Low-power operation 1.2 W (typ) DSPLLTM based clock multiplier LVDS/LVPECL compatible unit w/ selectable loop filter interface bandwidths Single supply 1.8 V operation Integrated limiting amplifier 15 x 15 mm BGA package Loss-of-signal (LOS) alarm Diagnostic and line loopbacks SI5100 Bottom View Ordering Information: See page 35. Applications SONET/SDH transmission systems Optical transceiver modules SONET/SDH test equipment Description The SI5100 is a complete low-power transceiver for high-speed serial communication systems operating between OC-48 and 2.7 Gbps. The receive path consists of a fully-integrated limiting amplifier, clock and data recovery unit (CDR), and 1:16 deserializer. The transmit path combines a low-jitter clock multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories' DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long-haul applications, programmable slicing and sample phase adjustment are supported. The SI5100 operates from a single 1.8 V supply over the industrial temperature range (-20 to 85 C). Functional Block Diagram SLICELVL PHASEADJ 1:16 DEMUX RXDOUT[15:0] Diagnostic Loopback RXCLK / 16:1 MUX TXDOUT TXDIN[15:0] RXDIN Limiting AMP CDR Line Loopback TXCLKOUT M DSPLLT TX CMU TXCLK16IN REFCLK BWSEL[1:0] Rev. 1.1 7/04 Copyright (c) 2004 by Silicon Laboratories SI5100 SI5100 2 Rev. 1.1 SI5100 TABLE O F CONTENTS Section Page 1. SI5100 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. SI5100 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. Receiver Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.3. Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4. Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5. Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6. Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7. Receive Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1. DSPLLTM Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2. Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 7. Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8. Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 12. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 13. Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 14. Internal Pullups and Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 16. SI5100 Pinout: 195 BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17. Pin Descriptions: SI5100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 20. 15x15 mm 195L CBGA Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.1 3 SI5100 1. SI5100 Detailed Block Diagram SLICEMODE SLICELVL PHASEADJ LTR RXLOL RXMSBSEL RXSQLCH DLBK LOS RXDIN Lim iting Amp CDR 1:16 DEMUX 32:16 MUX RXDOUT[15:0] LOSLVL LOS RXAMPMON RXCLK1DSBL RXCLK1 RXCLK2 RXCLK2DSBL RXCLK2DIV TXSQLCH FIFOERR FIFORST TXDOUT 16:1 MUX FIFO 32:16 MUX TXDIN[15:0] TXCLKDSBL TXCLKOUT TXCLK16OUT TXCLK16IN TXLOL CMU REFCLK TXMSBSEL BWSEL[1:0] REFRA TE LPTM LLBK REFSEL LLBK 4 Rev. 1.1 SI5100 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL Output Supply Voltage SI5100 Supply Voltage Symbol TA VDDIO VDD Test Condition Min* -20 1.71 1.71 Typ 25 -- 1.8 Max* 85 3.47 1.89 Unit C V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. V SIGNAL + Differential VICM, VOCM SIGNAL - I/Os 0V (SIGNAL +) - (SIGNAL -) Differential Voltage Swing VID,VOD (VID = 2 VISE) Differential Peak-to-Peak Voltage t VI VISE, VOSE Single Ended Voltage Figure 1. Differential Voltage Measurement (RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN) tcd TXDOUT, TXDIN tCP TXCLKOUT, TXCLK16IN tCH RXDOUT RXCLK1 tcq1 tcq2 Figure 2. Data to Clock Delay Rev. 1.1 5 SI5100 80% 20% tF tR Figure 3. Rise/Fall Time Measurement Table 2. DC Characteristics (VDD = 1.8 V 5%, TA = -20 to 85 C) All Differential IOs Parameter Supply Current Symbol Test Condition IDD Full Duplex Line/Diagnostic Loopback Full Duplex Line/Diagnostic Loopback VREF driving 10 k load Min -- Typ 680 760 1.2 1.4 1.25 0.5 -- 0.9 1200 -- -- 1.2 -- -- Max 760 830 1.4 1.6 1.29 0.6 20001 1.1 1400 2.5 2400 2.4 -- 1.475 Unit mA Power Dissipation PD -- W Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input Voltage Swing (RXDIN) (@ Bit Error Rate of 10-12) Common Mode Output Voltage (TXDOUT, TXCLKOUT) Differential Output Voltage Swing (TXDOUT,TXCLKOUT), Differential PK-PK LVPECL Input Voltage Level (REFCLK) LVPECL Input Voltage Swing, Differential PK-PK (REFCLK) LVDS Input Voltage Level (TXDIN,TXCLK16IN) LVDS Input Voltage, Differential PK-PK (TXDIN,TXCLK16IN) LVDS Output Voltage Level (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) LVDS Output Voltage, Differential PK-PK (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) VREF VICM VID VOCM VOD VI VID VI VID VO 1.21 0.4 V V mVPPD V mVPPD V mVPPD V mVPPD V Figure 1 30 0.7 Figure 1 1000 0.8 Figure 1 250 .8 2002 100 Load Line-to-Line 100 Load Line-to-Line, Figure 1 0.925 VOD 5502 650 800 mVPPD Notes: 1. Voltage on either RXDIN+ or RXDIN- should not exceed 1000 mVPP (single-ended). 2. LVDS differential voltages are for a 16-bit parallel data operation of the multiplexer/demultiplexer (MODE 16 = 1). 6 Rev. 1.1 SI5100 Table 2. DC Characteristics (Continued) (VDD = 1.8 V 5%, TA = -20 to 85 C) Parameter LVDS Common Mode Output Voltage (RXDOUT,RXCLK1,RXCLK2,TXCLK16OUT) Input Impedance (RXDIN) LVDS and LVPECL Input Impedance (TXDIN, TXCLK16IN, REFCLK) CML Output Impedance (TXDOUT, TXCLKOUT) LVDS Output Impedance (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) Output Current Short to GND (RXDOUT,RXCLK1,RXCLK2, TXCLK16OUT) Output Current Short to VDD (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) LVTTL Input Voltage Low LVTTL Input Voltage High LVTTL Input Impedance LVTTL Output Voltage Low (IOUT = 2 mA) LVTTL Output Voltage High (IOUT = 2 mA) RXAMPMON Output Impedance LOS/SLICELVL/PHASEADJ Input Impedance Symbol Test Condition VCM RIN RIN ROUT ROUT Each input to common mode Each input to common mode Each output to common mode Each output to common mode Min 1.125 42 45 45 45 Typ 1.2 50 55 55 55 Max 1.275 58 65 65 65 Unit V ISC(-) -- 12 40 mA ISC(+) -8 -6 -- mA VIL2 VIH2 RIN VOL2 VOH2 ROUT RIN VDDIO = 1.8-3.3 V VDDIO = 1.8-3.3 V -0.3 0.65 VDDIO 10 -- -- -- -- -- 6 -- 0.35 VDDIO VDDIO + 0.3 -- 0.4 -- 8 -- V V k V V k k VDDIO = 1.8-3.3 V -- VDDIO = 1.8-3.3 V VDDIO - 0.45 4 100 Notes: 1. Voltage on either RXDIN+ or RXDIN- should not exceed 1000 mVPP (single-ended). 2. LVDS differential voltages are for a 16-bit parallel data operation of the multiplexer/demultiplexer (MODE 16 = 1). Rev. 1.1 7 SI5100 Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2) (VDD = 1.8 V 5%, TA = -20 to 85 C) Parameter Input Data Rate (RXDIN) Output Clock Frequency (RXCLK1) Output Clock Frequency (RXCLK2) Symbol Test Condition fclkout fclkout Duty Cycle (RXCLK1, RXCLK2) Output Rise and Fall Times (RXCLK1, RXCLK2, RXDOUT) Data Invalid Prior to RXCLK1 Data Invalid After RXCLK1 Input Return Loss (RXDIN) LOS Threshold1, SLICEMODE = 0 LOS Threshold Error1, SLICEMODE = 0 LOS Threshold2, SLICEMODE = 1 LOS Threshold Error2, SLICEMODE = 1 RXDIN > 30 mV Slice Voltage3, SLICEMODE = 0 Slice Voltage as Percentage of Differential Input Voltage Swing (RXDIN), SLICEMODE = 14 Sample Phase5 RXAMPMON Voltage Range RXAMPMON Voltage Error Notes: 1. See Figure 4 on page 16. 2. See Figure 5 on page 17. 3. See Figure 6 on page 17. 4. See Figure 7 on page 18. 5. See Figure 8 on page 18. MODE16 = 1 MODE16 = 0 MODE16 = 1, RXCLK2DIV = 1 MODE16 = 1, RXCLK2DIV = 0 MODE16 = 0, RXCLK2DIV = 1 MODE16 = 0, RXCLK2DIV = 0 tch/tcp, Figure 2 Figure 3 Figure 2 Figure 2 1.25 GHz 2.5 GHz LOSLVL = 0-350 mV Min 2.41 -- -- -- -- -- -- 45 Typ -- 155 622 155 38.9 622 155 -- Max 2.7 167 675 169 42.2 675 169 55 Unit Gbps MHz MHz % ps ps ps dB dB mV % mV % tR,tF tcq1 tcq2 SII VLOS 100 -- -- -- -- 0 -- 175 -- -- -12 -10 -- -- -- -- 250 200 200 -- -- 250 30 60 50 VLOS LOSLVL = 0-500 mV 0 -- VLEVEL VLEVEL SLICELVL = 350 mV SLICELVL = 650 mV SLICELVL = 250 mV SLICELVL = 750 mV PHASEADJ = 200 mV PHASEADJ = 800 mV RXDIN = 0-1000 mVPPD -- -- -- -- -- -- 0 -- -50 40 -25 18 -25 25 -- -- -- -- -- -- -- -- 550 50 mV mV % % ps ps mV % 8 Rev. 1.1 SI5100 Table 4. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT) (VDD = 1.8 V 5%, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit TXCLKOUT Frequency TXCLKOUT Duty Cycle Output Rise Time (TXCLKOUT, TXDOUT) Output Fall Time (TXCLKOUT, TXDOUT) TXCLKOUT to TXDOUT Delay Output Return Loss TXCLK16OUT Frequency TXCLK16OUT Duty Cycle TXCLK16OUT Rise & Fall Times TXDIN Setup to TXCLK16IN TXDIN Hold from TXCLK16IN TXCLK16IN Frequency TXCLK16IN Duty Cycle TXCLK16IN Rise & Fall Times fclkout tch/tcp, Figure 2 tR tF tCD Figure 3 Figure 3 Figure 2 100 kHz-2.5 GHz 2.5-4.0 GHz fCLKOUT MODE16 = 1 MODE16 = 0 tch/tcp, Figure 2 tR, tF tDSIN tDHIN fCLKIN MODE16 = 1 MODE16 = 0 tch/tcp, Figure 2 tR, tF 2.41 40 -- -- -42 -- -- -- -- 40 100 -- -- -- -- 40 100 -- 50 50 50 -- -12 -10 155 622 -- 175 -- -- 155 622 -- -- 2.7 60 75 75 -22 -- -- 169 675 60 250 300 300 169 675 60 300 GHz % ps ps ps dB dB MHz % ps ps ps MHz % ps Rev. 1.1 9 SI5100 Table 5. AC Characteristics (Receiver PLL)1 (VDD = 1.8 V 5%, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance (RXDIN = 100 mVPPD, PRBS31)2 JTOL(PP) f = 10 - 600 Hz f = 0.6 - 6 kHz f = 6 - 100 kHz f = 100 kHz-1 MHz f = 1-20 MHz 152 152 92 0.4 0.3 -- -- -- -- -- -- -- 155 78 50 -- 732 -- -- -- -- -- 2 169 84.4 60 100 860 UIPP UIPP UIPP UIPP UIPP ms MHz MHz % ppm ppm Acquisition Time Input Reference Clock Frequency (REFSEL = 1) Reference Clock Duty Cycle Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) TAQ RCFREQ RCDUTY RCTOL LOL REFRATE = 1 REFRATE = 0 -- -- 40 -100 610 LOCK -- 366 240 ppm Notes: 1. Bellcore specifications: GR-253-CORE, Issue 3, September 2000. 2. Instrument limited. 10 Rev. 1.1 SI5100 Table 6. AC Characteristics (Transmitter Clock Multiplier)1 (VDD = 1.8 V 5%, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Transfer Bandwidth (OC-48: 2.48832 Gbps) JBW BWSEL[1:0] = 00 BWSEL[1:0] = 01 BWSEL[1:0] = 10 BWSEL[1:0] = 11 BWSEL[1:0] = 00 BWSEL[1:0] = 01 BWSEL[1:0] = 10 BWSEL[1:0] = 11 Valid REFCLK REFRATE = 1 REFRATE = 0 -- -- -- -- -- -- -- -- -- -- -- -- 40 -100 -- -- -- -- -- -- -- -- 0.05 -- 155 78 -- -- 2.5 2.0 1.7 1.7 25.5 24.0 22.0 22.0 12 50 120 200 12 50 120 200 0.1 20 169 84.4 60 100 3.4 2.4 2.1 1.8 34 33 27 26 kHz kHz kHz kHz kHz kHz kHz kHz dB ms MHz % ppm mUIrms mUIrms mUIrms mUIrms mUIpp mUIpp mUIpp mUIpp Jitter Transfer Bandwidth (FEC: 2.66667 Gbps) JBW Jitter Transfer Peaking Acquisition Time TAQ Input Reference Clock Frequency RCFREQ Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance Random rms Jitter Generation, TXCLKOUT (PRBS 31)2 RCDUTY RCTOL JGEN(rms) BWSEL[1:0] = 00 BWSEL[1:0] = 01 BWSEL[1:0] = 10 BWSEL[1:0] = 11 BWSEL[1:0] = 00 BWSEL[1:0] = 01 BWSEL[1:0] = 10 BWSEL[1:0] = 11 -- -- -- -- -- -- -- -- Total Peak-to-Peak Jitter Generation, TXCLKOUT, TXDOUT (PRBS 31)2 JGEN(pp) Notes: 1. Bellcore specifications: GR-253-CORE, Issue 3, September 2000. 2. Full duplex; REFCLK = 155 MHz. Rev. 1.1 11 SI5100 Table 7. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage LVTTL I/O Supply Voltage Differential Input Voltage (LVDS Input) Differential Input Voltage (LVDS Output) Differential Input Voltage (LVTTL Input) Differential Input Voltage (LVTTL Output) Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM (2.5 GHz Pins) ESD HBM Tolerance (100 pF, 1.5 k) VDD VDDIO VDIF VDIF VDIF VDIF TJCT TSTG -0.5 to 2.2 -0.5 to 4.0 5 -0.3 to (VDD+ 0.3) 2.4 5 50 -55 to 150 -55 to 150 1 2 V V V V V V mA C C kV kV Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Restrict functional operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Table 8. Thermal Characteristics Parameter Symbol JA Test Condition Value Unit Thermal Resistance Junction to Ambient Still Air 20 C/W 12 Rev. 1.1 SI5100 3. SI5100 Typical Application Schematic LVTTL Control Inputs TXMSBEL RXMSBSEL RXCLK2DSBL RXCLK1DSBL SLICEMODE RXCLK2DIV TXCLKDSBL BWSEL[1:0] REFRATE RXSQLCH TXSQLCH MODE16 REFSEL LPTM DLBK LLBK LTR RXAMPMON FIFORST FIFOERR TXLOL RESET 0.1 F RXDIN Amplitude Monitor Analog Output FIFO Over/Underflow Loss-of-Lock Indicator Loss-of-Signal Indicator LVDS Recovered Parallel Data LVDS Recovered Low-Speed Clock High-Speed Serial Data Output 0.1 F RXLOL LOS High-Speed Serial Input LVPECL Reference Clock LVDS Parallel Data Input 16 RXDIN SI5100 REFCLK RXDOUT[15:0] RXCLK1 RXCLK2 16 0.1 F TXDIN[15:0] TXDOUT LVDS Data Clock Input TXCLKOUT TXCLK16IN TXCLK16OUT PHASEADJ SLICELVL RXREXT TXREXT VREF GND VDD High-Speed Clock Output Low-Speed Clock Output Voltage Reference Output (1.25 V) LOSLVL 3.091 k 1% 3.091 k 1% VDD Power Supply Filtering* Loss-of-Signal Data Slice Level Set Level Set Sampling Phase Level Set Note* See "Power Supply Filtering" on page 21. Rev. 1.1 13 SI5100 4. Functional Description The SI5100 transceiver is a low-power fully-integrated serializer/deserializer that provides significant margin to all SONET/SDH jitter specifications. The device operates from 2.41-2.7 Gbps making it suitable for OC48/STM-16 applications and OC-48/STM-16 applications that use 255/238 or 255/237 forward error correction (FEC) coding. The low-speed receive/transmit interface uses a low-power parallel LVDS interface compatible with LVPECL. The receiver signal amplitude monitoring circuit is also used in the generation of the loss-of-signal alarm (LOS). 5.2.2. Loss-of-Signal Alarm (LOS) The SI5100 can be configured to activate a loss-ofsignal alarm output (LOS) when the RXDIN input amplitude drops below a programmable threshold level. An appropriate level of hysteresis prevents unnecessary switching on LOS. The LOS threshold level is set by applying a dc voltage to the LOSLVL input. The mapping of the voltage on the LOSLVL pin to the LOS threshold level depends on the state of the SLICEMODE input. (The SLICEMODE input is used to select either absolute slice mode or proportional slice mode operation.) The LOSLVL mapping for absolute slice mode (SLICEMODE = 0) is given in Figure 4. The linear region of the assert can be approximated by the following equation: V LOS V LOSLVL x .958 5. Receiver The receiver within the SI5100 includes a precision limiting amplifier, a jitter-tolerant clock and data recovery unit (CDR), and a 1:16 demultiplexer. Programmable data slicing level and sampling phase adjustment are provided to support bit-error-rate (BER) optimization for long-haul applications. 5.1. Receiver Differential Input Circuitry The receiver serial input provides proper termination and biasing through two resistor dividers internal to the device. The active circuitry has high-impedance inputs and provides sufficient gain for the clock and data recovery unit to recover the serial data. The input bias levels are optimized for jitter tolerance and input sensitivity and are typically not dc compatible with standard I/Os; simply ac couple the data lines as shown in Figure 10 on page 22. Equation 2 where VLOS is the differential PK-PK LOS threshold referred to the RXDIN input, and VLOSLVL is the voltage applied to the LOSLVL pin. The linear region of the de-assert curve can be approximated by the following equation: V LOS V LOSLVL x .762 5.2. Limiting Amplifier The SI5100 incorporates a limiting amplifier with sufficient gain to directly accept the output of transimpedance amplifiers. The limiting amplifier provides sufficient gain to fully saturate with input signals that are greater than 30 mV peak-to-peak differential. In addition, input signals up to 2 V peak-to-peak differential do not cause any performance degradation. 5.2.1. Receiver Signal Amplitude Monitoring The SI5100 limiting amplifier includes circuitry that monitors the amplitude of the receiver differential input signal (RXDIN). The RXAMPMON output provides an analog output signal that is proportional to the input signal amplitude. The signal is enabled when slice mode is asserted. The voltage on the RXAMPMON output is nominally equal to one-half of the differential peak-to-peak signal amplitude of RXDIN as shown in Equation 1: V RXAMPMON V RXDIN ( PP ) x .566 Equation 3 The LOSLVL mapping for proportional slice mode (SLICEMODE = 1) is given in Figure 6 on page 17. The linear region of the assert can be approximated by the following equation: V LOS V LOSLVL x .61 Equation 4 where VLOS is the differential pk-pk LOS threshold referred to the RXDIN input, and VLOSLVL is the voltage applied to the LOSLVL pin. The linear region of the de-assert curve can be approximated by the following equation: V LOS V LOSLVL x .72 Equation 5 Equation 1 The LOS detection circuitry is disabled by tieing the LOSLVL input to VREF. This forces the LOS output high. 14 Rev. 1.1 SI5100 5.2.3. Slice Level Adjustment 5.3.1. Sample Phase Adjustment The limiting amplifier allows adjustment of the 0/1 decision threshold, or slice level, to allow optimization of bit-error-rates (BER) for demanding applications, such as long-haul links. The SI5100 provides two different modes of slice level adjustment: Absolute slice mode and proportional slice mode. The mode is selected using the SLICEMODE input. In either mode, the slice level is set by applying a dc voltage to the SLICELVL input. The mapping of the voltage on the SLICELVL pin to the 0/1 decision threshold voltage (or slice voltage) depends on the selected mode of operation. The SLICELVL mapping for absolute slice mode (SLICEMODE = 0) is given in Figure 6. The linear region of this curve can be approximated by the following equation: V LEVEL ( ( V SLICELVL - ( VREF x 0.4 ) ) x 0.375 ) - 0.005 In applications where data eye distortions are introduced by the transmission medium, it may be desirable to recover data by sampling at a point that is not at the center of the data eye. The SI5100 provides a sample phase adjustment capability that allows adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of approximately 22 ps relative to the center of the incoming NRZ bit period. The sample phase is set by applying a dc voltage to the PHASEADJ input. The mapping of the voltage present on the PHASEADJ input to the sample phase sampling offset is given in Figure 8 on page 18. The linear region of this curve can be approximated by the following equation: Phase Offset 85 ps/V x ( V PHASEADJ - ( 0.4 x VREF ) ) Equation 6 Equation 8 where VLEVEL is the effective slice level referred to the RXDIN input, VSLICELVL is the voltage applied to the SLICELVL pin, and VREF is the reference voltage provided by the SI5100 on the VREF output pin (nominally 1.25 V). The SLICELVL mapping for proportional slice mode (SLICEMODE = 1) is given in Figure 7 on page 18. The linear region of this curve can be approximated by the following equation: V LEVEL [ ( V SLICELVL - ( VREF x 0.4 ) ) x ( V RXDIN ( PP ) x 0.95 ) ] - [ 0.03 x V RXDIN ( PP ) ] Equation 7 where VLEVEL is the effective slice level referred to the RXDIN input; VSLICELVL is the voltage applied to the SLICELVL pin; VREF is the reference voltage provided by the SI5100 on the VREF output pin, and VRXDIN(PP) is the peak-to-peak voltage level of the receive data signal applied to the RXDIN input. The slice level adjustment function can be disabled by tieing the SLICELVL input the VREF. When slice level adjustment is disabled, the effective slice level is set to 0 mV relative to internally biased input common mode voltage for RXDIN. 5.3. Clock and Data Recovery (CDR) The SI5100 uses an integrated CDR to recover clock and data from a non-return to zero (NRZ) signal input on RXDIN. The recovered clock is used to regenerate the incoming data by sampling the output of the limiting amplifier at the center of the NRZ bit period. where Phase Offset is the sampling offset in picoseconds from the center of the data eye; VPHASEADJ is the voltage applied to the PHASEADJ pin, and VREF is the reference voltage provided by the SI5100 on the VREF output pin (nominally 1.25 V). A positive phase offset adjusts the sampling point to lead the default sampling point (the aligned center of the data eye) and a negative phase offset adjusts the sampling point to lag the default sampling point. Data recovery using a sampling phase offset is disabled by tieing the PHASEADJ input to VREF. This forces a phase offset of 0 ps to be used for data recovery. 5.3.2. Receiver Lock Detect The SI5100 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. This circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock. The SI5100 uses either REFCLK or TXCLK16IN as the reference clock input signal depending on the state of the REFSEL input. If the (divided) recovered clock frequency deviates from that of the reference clock by more than the amount specified in Table 5 on page 10, the CDR is declared out of lock, and the loss-of-lock (RXLOL) pin is asserted. In this state, the CDR attempts to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (RXCLK1 and RXCLK2) drifts over a range of approximately 1000 ppm relative to the supplied reference clock unless LTR is asserted. The RXLOL output remains asserted until the frequency of the (divided) recovered clock differs from the reference clock frequency by less Rev. 1.1 15 SI5100 than the amount specified in Table 5 on page 10. The RXLOL output is asserted automatically if a valid reference clock is not detected. The RXLOL output is also asserted whenever the loss of signal alarm (LOS) is active, provided that the LTR input is set high (i.e. provided that the device is not configured for lock-to-reference mode). 5.3.3. Lock-to-Reference The lock-to-reference (LTR) input can be utilized to ensure the presence of a stable output clock during a loss-of-signal alarm (LOS). When LTR is asserted, the CDR is prevented from phase locking to the data signal and the CDR locks the RXCLKOUT1 and RXCLKOUT2 outputs to the reference clock. In typical applications, the LOS output is tied to the LTR input to force a stable output clock during a loss-of-signal condition. on RXDOUT[3:0]. 5.4.1. Serial Input to Parallel Output Relationship The SI5100 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[15:0]. The mapping of the receive bits to the output data word is controlled by the RXMSBSEL input. When RXMSBSEL is set low, the first bit received is output on RXDOUT0, and the following bits are output in order on RXDOUT1 through RXDOUT15 (RXDOUT1 through RXDOUT3 if MODE16 = 0). When RXMSBSEL is set high, the first bit received is output on RXDOUT15 (RXDOUT3), and the following bits are output in order on RXDOUT14 (RXDOUT2) through RXDOUT0. 5.5. Voltage Reference Output The SI5100 provides an output voltage reference that can be used by external circuitry to set the LOS threshold, slicing level, or sampling phase adjustment input voltage levels. One possible implementation uses a resistor divider to set the control voltage for the LOSLVL, SLICELVL, or PHASEADJ inputs. An alternative is the use of a digital-to-analog converters (DACs) to set the control voltages. With this approach, VREF is used to set the range of the DAC outputs. The voltage on the VREF output is nominally 1.25 V. 5.4. Deserialization The SI5100 deserializes the high-speed data from the CDR and outputs the deserialized data on the 16-bit parallel data bus RXDOUT[15:0]. The demultiplexer used for deserialization is configured by the MODE16 pin to output either 4-bit or 16-bit data words on the bus. The data words are output on RXDOUT[15:0] with the rising edge of RXCLK1. When the demultiplexer is configured to output 4-bit data words, the data is output 350 300 250 200 VLOS (mV) = 58 .9 L LV OS L Assert DeAssert L LV OS 2L V S LO 150 =. 76 V LOS 100 50 0 0 0.05 0.1 0.15 0.2 LOSLV (V) 0.25 0.3 0.35 0.4 Figure 4. Typical LOSLVL Transfer Curve, Absolute Slice Mode (SLICEMODE = 0) 16 Rev. 1.1 SI5100 LOSLVL Transfer Curve (Proportional Slice Mode) 350 300 250 VLOS (mV) 200 V LOS L SLV 2 LO = .7 L SLV 1 LO = .6 150 V LOS 100 50 0 0 0.05 0.1 0.15 0.2 0.25 LOSLVL (V) LOS Assert Threshold LOS De-assert Threshold 0.3 0.35 0.4 0.45 0.5 Figure 5. Typical LOSLVL Transfer Curve, Proportional Slice Mode (SLICEMODE = 1) SLICELVL Transfer Curve (Absolute Slice Mode) 60 40 Slice Adjustment (mV) 20 0 -20 -40 -60 0.35 0.4 0.45 0.5 SLICELVL (V) 0.55 0.6 0.65 Figure 6. Typical SLICELVL Transfer Curve, Absolute Slice Mode (SLICEMODE = 0) Rev. 1.1 17 SI5100 SLICELVL Transfer Curve (Proportional Slice Mode) 30 20 Slice Adjustment (% of RXDIN) 10 0 -10 -20 -30 0.25 0.3 0.35 0.4 0.45 0.5 SLICELVL (V) 0.55 0.6 0.65 0.7 0.75 Figure 7. Typical SLICELVL Transfer Curve, Proportional Slice Mode (SLICEMODE = 1) PHASEADJ Transfer Curve 40 30 20 Phase Adjustment (ps) 10 0 -10 -20 -30 -40 0.2 0.3 0.4 0.5 PHASEADJ (Volts) 0.6 0.7 0.8 Figure 8. Typical PHASEADJ Transfer Curve 18 Rev. 1.1 SI5100 5.6. Auxiliary Clock Output To support the widest range of system timing configurations, The Si5601/Si5602 provides a primary clock output (RXCLK1) and a secondary clock output (RXCLK2). The RXCLK2 output can be configured to provide a clock that is 1/16th or 1/64th the frequency of the high-speed recovered clock. The divide ratio which determines the RXCLK2 output frequency is selected by RXCLK2DIV. 6.1. DSPLLTM Clock Multiplier Unit The SI5100's clock multiplier unit (CMU) uses Silicon Laboratories proprietary DSPLL technology to achieve optimal jitter performance. The DSPLL implementation utilizes a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). The DSPLL implementation requires no external loop filter components. Eliminating sensitive noise entry points makes the DSPLL implementation less susceptible to board-level noise sources and makes SONET/SDH jitter compliance easier to attain in the application. The transmit CMU multiplies the frequency of the selected reference clock up to the serial transmit data rate. The TXLOL output signal provides an indication of the transmit CMU lock status. When the CMU has achieved lock with the selected reference, the TXLOL output is deasserted (driven high). The TXLOL signal is asserted, indicating a transmit CMU loss-of-lock condition when a valid clock signal is not detected on the selected reference clock input. The TXLOL signal is also asserted during the transmit CMU frequency calibration. Calibration is performed automatically when the SI5100 is powered on, when a valid clock signal is detected on the selected reference clock input following a period when no valid clock was present, or when the frequency of the selected reference clock is outside of the transmit CMU's PLL lock range, or after RESET is deasserted. 6.1.1. Programmable Loop Filter Bandwidth The digitally-implemented loop filter allows for four transmit CMU loop bandwidth settings that provide wideband or narrowband jitter transfer characteristics. The filter bandwidth is selected via the BWSEL[1:0] control inputs. The loop bandwidth choices are listed in Table 6. Unlike traditional PLL implementations, changing the loop filter bandwidth of the SI5100 is accomplished without the need to change external component values. Lower loop bandwidth settings (Narrowband operation) make the SI5100 more tolerant to jitter on the reference clock source. As a result, circuitry used to generate and distribute the physical layer reference clocks can be simplified without compromising margin to the SONET/SDH jitter specifications. Higher loop bandwidth settings (Wideband operation) are useful in applications where the reference clock is provided by a low jitter source, such as the Si5364 Clock Synchronization IC or Si5320 Precision Clock 5.7. Receive Data Squelch During some system error conditions, such as LOS, it may be desirable to force the receive data output to zero in order to avoid propagation of erroneous data into the downstream electronics. The SI5100 provides a data squelching control input, RXSQLCH, for this purpose. When the RXSQLCH input is low, the data outputs, RXDOUT[15:0], are forced to a zero state. The RXSQLCH input is ignored when the device is operating in diagnostic loopback mode (DLBK = 0). 6. Transmitter The transmitter consists of a low-jitter clock multiplier unit (CMU) with a serializer that operates in either a 16:1 or 4:1 configuration. The CMU uses a phaselocked loop (PLL) architecture based on Silicon Laboratories' proprietary DSPLL technology. This technology generates low jitter clock and data outputs that provide significant margin to the SONET/SDH specifications. The DSPLL architecture also utilizes a digitally-implemented loop filter that eliminates the need for external loop filter components. As a result, sensitive noise coupling nodes that typically degrade jitter performance in crowded PCB environments are removed. The DSPLL also reduces the complexity and relaxes the performance requirements for reference clock distribution circuitry for OC-48/STM-16 optical port cards. The DSPLL provides selectable wideband and narrowband loop filter settings that allow the jitter attenuation characteristics of the CMU to be optimized for the jitter content of the supplied reference clock. This allows the CMU to operate with reference clocks that have relatively high jitter content. Unlike traditional analog PLL implementations, the loop filter bandwidth of the SI5100 transmitter CMU is controlled by a digital filter inside the DSPLL circuit allowing the bandwidth to be changed without changing any external component values. Rev. 1.1 19 SI5100 Multiplier/Jitter Attenuator IC. Wideband operation allows the DSPLL to more closely track the precision reference source resulting in the best possible jitter performance. (TXDIN3) is transmitted first, followed in order by TXDIN14 (TXDIN2) through TXDIN0. This feature can simplify printed circuit board (PCB) routing in applications where ICs are mounted on both sides of the PCB. 6.2.3. Transmit Data Squelch To prevent the transmission of corrupted data into the network, the SI5100 provides a control pin that can be used to force the high-speed serial data output TXDOUT to zero. When the TXSQLCH input is set low, the TXDOUT signal is forced to a zero state. The TXSQLCH input is ignored when the device is in line loopback mode (LLBK = 0). 6.2.4. Clock Disable The SI5100 provides a clock disable pin, TXCLKDSBL, that can be used to disable the high-speed serial data clock output, TXCLKOUT. When the TXCLKDSBL pin is asserted, the positive and negative terminals of CLKOUT are internally tied to 1.5 V through 50 onchip resistors. This feature can be used to reduce power consumption in applications that do not use the high-speed transmit data clock. 6.2. Serialization The SI5100 serialization circuitry is comprised of a FIFO and a parallel to serial shift register. The device can be configured to serialize either 4-bit data words input on TXDIN[3:0] or 16-bit data words input on TXDIN[15:0]. The 4-bit or 16-bit configuration is selected using the MODE16 input. Low-speed data on the parallel input bus is latched into the FIFO on the rising edge of TXCLK16IN. Data is clocked out of the FIFO and into the shift register by TXCLK16OUT. The high-speed serial data stream TXDOUT is clocked out of the shift register by TXCLKOUT. The TXCLK16OUT clock is provided as an output signal to support either 4-bit or 16-bit word transfers between the SI5100 and upstream devices using a counter clocking scheme. 6.2.1. Input FIFO The SI5100 transmit FIFO decouples the timing of the data transferred into the FIFO via TXCLK16IN from the data transferred into the shift register via TXCLK16OUT. The FIFO is eight parallel words deep and accommodates static phase delay that may be introduced between TXCLK16OUT and TXCLK16IN in counter clocking schemes. Furthermore, the FIFO accommodates a bounded phase drift, or wander, between TXCLK16IN and TXCLK16OUT of up to three parallel data words. The FIFO circuitry indicates an overflow or underflow condition by asserting the FIFOERR signal. This output can be used to re-center the FIFO read/write pointers by tieing it directly to the FIFORST input. The FIFORST signal causes re-centering of the FIFO read/write pointers. The SI5100 also automatically recenters the read/write pointers after the device is powered on, after an external reset via the RESET input, and each time the DSPLL transitions from an outof-lock state to a locked state (when TXLOL transitions from low to high). 6.2.2. Parallel Input To Serial Output Relationship The SI5100 provides the capability to select the order in which the data received on the parallel input bus, TXDIN[15:0], is transmitted serially on the high-speed serial data output, TXDOUT. Data on the parallel bus is transmitted MSB first or LSB first depending on the setting of the TXMSBSEL input. When TXMSBSEL is set low, TXDIN0 is transmitted first, followed in order by TXDIN1 through TXDIN15 (TXDIN1 through TXDIN3 if MODE16 = 0). When TXMSBSEL is set high, TXDIN15 7. Loop Timed Operation The SI5100 can be configured to provide SONET/SDH compliant loop timed operation. When the LPTM input is set low, the transmit clock and data timing is derived from the CDR recovered clock output. This is achieved by dividing down the recovered clock and using it as a reference source for the transmit CMU. This results in transmit clock and data signals that are locked to the timing recovered from the received data path. A narrowband loop filter setting is recommended for this mode of operation. 8. Diagnostic Loopback The SI5100 provides a diagnostic loopback mode that establishes a loopback path from the serializer output to the deserializer input. This provides a mechanism for looping back data input via the low-speed transmit interface, TXDIN[15:0], to the low-speed receive data interface, RXDOUT[15:0]. This mode is enabled when the DLBK input is set low. Note: Setting both DLBK and LLBK low simultaneously is not supported. 20 Rev. 1.1 SI5100 9. Line Loopback The SI5100 provides a line loopback mode that establishes a loopback path from the high-speed receive input to the high-speed transmit output. This provides a mechanism for looping back the high-speed clock and data recovered from RXDIN to the transmit data output, TXDOUT, and clock, TXCLKOUT. This mode is enabled when the LLBK input is set low. Note: Setting both DLBK and LLBK low simultaneously is not supported. 12. Reset The SI5100 is reset by holding the RESET pin low for at least 1 s. When RESET is asserted, the input FIFO pointers are reset and the digital control circuitry is initialized. When RESET transitions high to start normal operation, the transmit CMU calibration is performed. 13. Transmit Differential Output Circuitry The SI5100 utilizes a current-mode logic (CML) architecture to drive the high-speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 9. In applications with direct dc coupling, the 0.1 F capacitors can be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2. 10. Bias Generation Circuitry The SI5100 uses two external resistors, RXREXT and TXREXT, to set internal bias currents for the receive and transmit sections of the device, respectively. The external resistors allow precise generation of bias currents, which can significantly reduce power consumption. The bias generation circuitry requires two 3.09 k (1%) resistors each connected between RXREXT and GND and between TXREXT and GND. 14. Internal Pullups and Pulldowns On-chip 30 k resistors are used to individually set the LVTTL inputs if these inputs are left unconnected. The specific default state of each input is enumerated in "Pin Descriptions: SI5100" on page 26. 11. Reference Clock The SI5100 supports operation with one of two possible reference clock sources. In the first configuration, an external reference clock is connected to the REFCLK input. The second configuration uses the parallel data clock, TXCLK16IN, as the reference clock source. The REFSEL input is used to select whether the REFCLK or the TXCLK16IN input are used as the reference clock. When REFCLK is selected as the reference clock source (REFSEL = 1), two possible reference clock frequencies are supported. The reference clock frequency provided on the REFCLK input can be either 1/16th or 1/32th the desired transceiver data rate. The REFCLK frequency is selected using the REFRATE input. The TXCLK16IN clock frequency is equal to either 1/4th or 1/16th the transceiver data rate depending on the state of the MODE16 input. When TXCLK16IN is selected as the reference clock source (REFSEL = 0), the REFRATE input has no effect. The CMU in the SI5100's transmit section multiplies the provided reference up to the serial transmit data rate. When the CMU has achieved lock with the selected reference, the TXLOL output is deasserted (driven high). The CDR in the receive section of the SI5100 uses the selected reference clock to center the receiver PLL frequency in order to speed lock acquisition. When the receive CDR locks to the data input, the RXLOL signal is deasserted (driven high). 15. Power Supply Filtering The transmitter-generated jitter is most sensitive to power supply noise below its PLL loop-bandwidth (BWSEL setting). The power supply noise of interest is bounded between the SONET/SDH generated jitter specification of 12 kHz (for 2.48832 Gbps) and the PLL loop-bandwidth. Integrated supply noise from 1/10th the SONET/SDH specification (1.2 kHz) to 10x the loopbandwidth should be suppressed to a level appropriate for each design. Below the PLL loop-bandwidth, the typical generated jitter due to supply noise is approximately 2.5 mUIpp per 1 mVrms; this parameter can be used as a guideline for calculating the output jitter and supply filtering requirements. The receiver does not place additional power supply constraints beyond those listed for the transmitter. Rev. 1.1 21 SI5100 1.5 V VDD 50 0.1 F Zo = 50 50 50 0.1 F Zo = 50 50 VDD 24 mA Figure 9. CML Output Driver Termination (TXCLKOUT, TXDOUT) 1.5 V 0.1 F 150 RXDIN+ 150 + RXDIN- 0.1 F 75 75 - Figure 10. Receiver Differential Input Circuitry 22 Rev. 1.1 SI5100 6.5 mA Out + ESD In + In _ 50 50 In _ In + Out _ ESD + _ 1.2 V 6.5 mA Figure 11. LVDS Driver Termination (RXDOUT, TXCLK16OUT) ESD 5 k In + 100 In _ 5 k ESD Common Mode Adjust Circuit Figure 12. LVDS Differential Input Circuitry Rev. 1.1 23 SI5100 16. SI5100 Pinout: 195 BGA 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [8]- [10]+ [8]+ [6]- [6]+ [4]- [4]+ [2]- [2]+ [0]- [0]+ RX CLK[1]- RX CLK[1]+ A RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [10]- [9]- [9]+ [7]- [7]+ [5]- [5]+ [3]- [3]+ [1]- [1]+ RX CLK[2]- RX CLK[2]+ GND B RXDOUT RXDOUT RXCLK2 RXREXT [12]+ [11]+ DIV RXAMP RXCLK2 MON RXSQLCH DSBL RSVD_ GND RSVD_ GND VREF SLICELVL LOSLVL GND GND C RXDOUT RXDOUT [12]- [11]- RXMSB SEL GND GND GND GND GND GND GND PHASEADJ RSVD_ GND GND RXDIN+ D RXDOUT RXDOUT [14]+ [13]+ SLICE MODE GND VDD VDD VDD VDD VDD VDD GND LTR GND RXDIN- E RXDOUT RXDOUT [14]- [13]- DLBK GND VDD VDD VDD VDD VDD VDD RXCLKIDSBL RXLOL GND GND F REF CLK+ RXDOUT MODE16 [15]+ GND VDD VDD VDD VDD VDD VDD RESET LOS GND TXCLKOUT+ G REF CLK- RXDOUT [15]- LLBK GND VDD VDD VDD VDD VDD VDD REFRATE VDDIO GND TXCLKOUT- H TXDIN [14]+ TXDIN [15]+ LPTM GND VDD VDD VDD VDD VDD VDD GND GND GND GND J TXDIN [14]- TXDIN [15]- TXCLK DSBL GND VDD VDD VDD VDD VDD VDD RSVD_ GND FIFOERR GND TXDOUT+ K TXDIN [12]+ TXDIN [13]+ REFSEL GND GND GND GND GND GND GND RSVD_ GND TXREXT GND TXDOUT- L TXDIN [12]- TXDIN [13]- TXSQLCH RSVD_ GND BWSEL1 TXMSB SEL RSVD_ GND BWSEL0 FIFORST TXLOL GND GND GND GND M TXDIN [11]+ TXDIN [11]- TXDIN [9]+ TXDIN [9]- TXDIN [7]+ TXDIN [7]- TXDIN [5]+ TXDIN [5]- TXDIN [3]+ TXDIN [3]- TXDIN [1]+ TXDIN [1]- TXCLK16 TXCLK16 IN+ IN- N TXDIN [10]+ TXDIN [10]- TXDIN [8]+ TXDIN [8]- TXDIN [6]+ TXDIN [6]- TXDIN [4]+ TXDIN [4]- TXDIN [2]+ TXDIN [2]- TXDIN [0]+ TXDIN [0]- TXCLK16 TXCLK16 OUT+ OUT- P Figure 13. SI5100 Pin Configuration (Bottom View) 24 Rev. 1.1 SI5100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A RX CLK[1]+ RX CLK[1]- RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [0]+ [0]- [2]+ [2]- [4]+ [4]- [6]+ [6]- [8]+ [8]- [10]+ B GND RX CLK[2]+ RX CLK[2]- RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [1]+ [1]- [3]+ [3]- [5]+ [5]- [7]+ [7]- [9]+ [9]- [10]- C GND GND LOSLVL SLICELVL VREF RSVD_ GND RSVD_ GND RXCLK2 RXAMP DSBL RXSQLCH MON RXREXT RXCLK2 RXDOUT RXDOUT DIV [11]+ [12]+ D RXDIN+ GND RSVD_ GND PHASE ADJ GND GND GND GND GND GND GND RXMSB SEL RXDOUT RXDOUT [11]- [12]- E RXDIN- GND LTR GND VDD VDD VDD VDD VDD VDD GND SLICE MODE RXDOUT RXDOUT [13]+ [14]+ F GND GND RXLOL RXCLK1 DSBL VDD VDD VDD VDD VDD VDD GND DLBK RXDOUT RXDOUT [13]- [14]- G TXCLKOUT+ GND LOS RESET VDD VDD VDD VDD VDD VDD GND MODE16 RXDOUT [15]+ REF CLK+ H TXCLKOUT- GND VDDIO REFRATE VDD VDD VDD VDD VDD VDD GND LLBK RXDOUT [15]- REF CLK- J GND GND GND GND VDD VDD VDD VDD VDD VDD GND LPTM TXDIN [15]+ TXDIN [14]+ K TXDOUT+ GND FIFOERR RSVD_ GND VDD VDD VDD VDD VDD VDD GND TXCLK DSBL TXDIN [15]- TXDIN [14]- L TXDOUT- GND TXREXT RSVD_ GND GND GND GND GND GND GND GND REFSEL TXDIN [13]+ TXDIN [12]+ M GND GND GND GND TXLOL FIFORST BWSEL0 RSVD_ GND TXMSB SEL BWSEL1 RSVD_ TXSQLCH GND TXDIN [13]- TXDIN [12]- N TXCLK16 TXCLK16 IN- IN+ TXDIN [1]- TXDIN [1]+ TXDIN [3]- TXDIN [3]+ TXDIN [5]- TXDIN [5]+ TXDIN [7]- TXDIN [7]+ TXDIN [9]- TXDIN [9]+ TXDIN [11]- TXDIN [11]+ P TXCLK16 TXCLK16 OUT- OUT+ TXDIN [0]- TXDIN [0]+ TXDIN [2]- TXDIN [2]+ TXDIN [4]- TXDIN [4]+ TXDIN [6]- TXDIN [6]+ TXDIN [8]- TXDIN [8]+ TXDIN [10]- TXDIN [10]+ Figure 14. SI5100 Pin Configuration (Transparent Top View) Rev. 1.1 25 SI5100 17. Pin Descriptions: SI5100 Alphabetically listed by name Pin Number(s) M10 M7 Name BWSEL1 BWSEL0 I/O I Signal Level LVTTL Description Transmit DSPLL Bandwidth Select. The inputs select loop bandwidth of the Transmit Clock Multiplier DSPLL as listed in Table 6. Note: Both inputs have an internal pulldown. F12 DLBK I LVTTL Diagnostic Loopback. When this input is low, the transmit clock and data are looped back for output on RXDOUT, RXCLK1 and RXCLK2. This pin should be held high for normal operation. Note: This input has an internal pullup. K3 FIFOERR O LVTTL FIFO Error. This output is asserted (driven low) when a FIFO overflow/underflow has occurred. This output is low until reset by asserting FIFORST. FIFO RESET. When this input is low, the read/write FIFO pointers are reset to their initial state. Note: This input has an internal pullup. M6 FIFORST I LVTTL B1, C1-2, D2, D5-11, E4, E11, E2, F11, F1-2, G11, G2, H11, H2, J11, J1-4, K11, K2, L5-11, L2, M1-4 H12 GND GND Supply Ground. Connect to system GND. Ensure a very low impedance path for optimal performance. LLBK I LVTTL Line Loopback. When this input is low, the recovered clock and data are looped back for output on TXDOUT, and TXCLKOUT. Set this pin high for normal operation. Note: This input has an internal pullup. G3 LOS O LVTTL C3 LOSLVL I Loss-of-Signal. This output is asserted (driven low) when the peak-to-peak signal amplitude on RXDIN is below the threshold set via LOSLVL. LOS Threshold Level. Applying an analog voltage to this pin allows adjustment of the Threshold used to declare LOS. Tieing this input to VREF disables LOS detection and forces the LOS output high. 26 Rev. 1.1 SI5100 Pin Number(s) Name I/O Signal Level Description Loop Timed Operation. When this input is set low, the recovered clock from the receiver is divided down and used as the reference source for the transmit CMU. The narrowband setting for the DSPLL CMU is sufficient to provide SONET compliant jitter generation and jitter transfer on the transmit data and clock outputs (TXDOUT,TXCLKOUT). Set this pin high for normal operation. Note: This input has an internal pullup. J12 LPTM I LVTTL E3 LTR I LVTTL Lock-to-Reference. When the LTR input is set low, the receiver PLL locks to the selected reference clock. This function can be used to force a stable output clock on the RXCLK1 and RXCLK2 outputs when no valid input data signal is applied to RXDIN. When the LTR input is set high, the receiver PLL locks to the RXDIN signal (normal operation). Note: This input has an internal pullup. G12 MODE16 I LVTTL D4 PHASEADJ I G14 H14 REFCLK+ REFCLK- I LVPECL MUX/DEMUX Mode. This input configures the multiplexer/demultiplexer to operate with either 4-bit or 16-bit parallel data words. When this input is set high, the device is configured for 16-bit parallel word transfers on RXDOUT[15:0] and TXDIN[15:0]. When this input is set low, the multiplexer/demultiplier operates with 4-bit word transfers on RXDOUT[3:0] and TXDIN[3:0]. Sampling Phase Adjust. Applying an analog voltage to this pin allows adjustment of the sampling phase across the data eye. Tieing this input to VREF nominally centers the sampling phase. Differential Reference Clock. This input is used as the SI5100 reference clock when the REFSEL input is set high (REFSEL = 1). The reference clock sets the operating frequency of the SI5100 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the SI5100 receiver CDR to center the PLL during lock acquisition, and as a reference for determination of the receiver lock status. The REFCLK frequency is either 1/16th or 1/32nd of the serial data rate (nominally 155 or 78 MHz, respectively). The REFCLK frequency is selected using the REFRATE input. Rev. 1.1 27 SI5100 Pin Number(s) H4 Name REFRATE I/O I Signal Level LVTTL Description Reference Clock Rate Select. The REFRATE input sets the frequency for the REFCLK input. When REFRATE is set high, the REFCLK frequency is 1/16th the serial data rate (nominally 155 MHz). When REFRATE is set low, the REFCLK frequency is 1/32nd the serial data rate (nominally 78 MHz). The REFRATE input has no effect when the REFSEL input is set low. Note: This input has an internal pullup. L12 REFSEL I LVTTL Reference Clock Selection. This input selects the reference clock source to be used by the SI5100 transmitter and receiver. The reference clock sets the operating frequency of the SI5100 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the SI5100 receiver CDR to center the PLL during lock acquisition, and as a reference for determination of the receiver lock status. When REFSEL = 0, the low-speed data input clock, TXCLK16IN, is used as the reference clock. When REFSEL = 1, the reference clock provided on REFCLK is used. Note: This input has an internal pullup. G4 RESET I LVTTL Device Reset. Forcing this input low for a at least 1 s causes a device reset. For normal operation, this pin should be held high. Note: This input has an internal pullup. C6-7, D3, K4, L4, M8, M11 C10 RSVD_GND RXAMPMON O Analog A2 A3 RXCLK1+ RXCLK1- O LVDS Reserved Tie to Ground. Must be connected directly to GND for proper operation. Receiver Amplitude Monitor. The RXAMPMON output provides an analog output signal that is proportional to the input signal amplitude. See Equation 1 for the relationship between the RXAMPMON output and RXDIN input. This signal is active when SLICEMODE is asserted. Differential Receiver Clock Output 1. The clock recovered from the signal present on RXDIN is divided down to the parallel output word rate and output on RXCLK1. In the absence of data, a stable clock on RXCLK1 can be maintained by asserting LTR. 28 Rev. 1.1 SI5100 Pin Number(s) B2 B3 Name RXCLK2+ RXCLK2- I/O O Signal Level LVDS Description Differential Receiver Clock Output 2. An auxiliary output clock is provided on this pin that is equivalent to, or a submultiple of, the output word rate. The divide factor used in generating RXCLK2 is set via RXCLK2DIV. RXCLK2 Clock Divider Select. This input selects the divide factor used to generate the RXCLK2 output. When this input is driven high, RXCLK2 is equal to the output word rate on RXDOUT. When driven low, RXCLK2 is 1/4th the output word rate. Note: This input has an internal pullup. RXCLK1 Disable. Setting this input low disables the RXCLK1 output. This is used to save power in applications that do not require the primary output clock. Note: This input has an internal pullup. C12 RXCLK2DIV I LVTTL F4 RXCLK1DSBL I LVTTL C8 RXCLK2DSBL I LVTTL RXCLK2 Disable. Setting this input low disables the RXCLK2 output. This saves power in applications that do not require an auxiliary clock. Note: This input has an internal pullup. D1 E1 RXDIN+ RXDIN- I High-Speed Differential Differential Receive Data Input. The receive clock and data signals RXCLK1, RXCLK2, and RXDOUT[15:0] are recovered from the high-speed data signal present on these pins. Rev. 1.1 29 SI5100 Pin Number(s) G13 H13 E14 F14 E13 F13 C14 D14 C13 D13 A14 B14 B12 B13 A12 A13 B10 B11 A10 A11 B8 B9 A8 A9 B6 B7 A6 A7 B4 B5 A4 A5 Name RXDOUT15+ RXDOUT15- RXDOUT14+ RXDOUT14- RXDOUT13+ RXDOUT13- RXDOUT12+ RXDOUT12- RXDOUT11+ RXDOUT11- RXDOUT10+ RXDOUT10- RXDOUT9+ RXDOUT9- RXDOUT8+ RXDOUT8- RXDOUT7+ RXDOUT7- RXDOUT6+ RXDOUT6- RXDOUT5+ RXDOUT5- RXDOUT4+ RXDOUT4- RXDOUT3+ RXDOUT3- RXDOUT2+ RXDOUT2- RXDOUT1+ RXDOUT1- RXDOUT0+ RXDOUT0- I/O O Signal Level LVDS Description Differential Parallel Receive Data Output. The data recovered from the signal present on RXDIN is demultiplexed and output as a 16-bit parallel word via RXDOUT[15:0]. The bit order for demultiplexing is selected by the RXMSBSEL input. The RXDOUT[15:0] outputs are aligned to the rising edge of RXCLK1. F3 RXLOL O LVTTL Receiver Loss-of-Lock. This output is asserted (driven low) when the recovered clock frequency deviates from the reference clock by the amount specified in Table 5 on page 10 (LOL). 30 Rev. 1.1 SI5100 Pin Number(s) D12 Name RXMSBSEL I/O I Signal Level LVTTL Description Receive Data Bus Bit Order Select. This determines the order of the received data bits on the output bus. When RXMSBSEL is set low, the first bit received is output on RXDOUT0 and the following bits are output in order on RXDOUT1 through RXDOUT15 (RXDOUT1 through RXDOUT3 if MODE16 = 0). When RXMSBSEL is set high, the first bit received is output on RXDOUT15 (RXDOUT3) and the following bits are output in order on RXDOUT14 (RXDOUT2) through RXDOUT0. Note: This input has an internal pulldown. C11 RXREXT Receiver External Bias Resistor. This resistor is used by the receiver circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor. C9 RXSQLCH I LVTTL Receiver Data Squelch. When this input is low the data on RXDOUT[15:0] is forced to a zero state. Set RXSQLCH high for normal operation. The RXSQLCH input is ignored when operating in diagnostic loopback mode (DLBK = 0). Note: This input has an internal pullup. C4 SLICELVL I E12 SLICEMODE I LVTTL Slicing Level Adjustment. Applying an analog voltage to this pin allows adjustment of the slicing level applied to the input data eye. Tying this input to VREF sets the slicing offset to 0. Slice Level Adjustment Mode. The SLICEMODE input is used to select the mode of operation for slicing level adjustment. When SLICEMODE = 0, absolute slice mode is selected. When SLICEMODE = 1, proportional slice mode is selected. Note: This input has an internal pulldown. N2 N1 TXCLK16IN+ TXCLK16IN- I LVDS Differential Transmit Data Clock Input. The rising edge of this input clocks data present on TXDIN into the device. TXCLK 16IN is also used as the SI5100 reference clock when the REFSEL input is set low. Rev. 1.1 31 SI5100 Pin Number(s) P2 P1 Name TXCLK16OUT+ TXCLK16OUT- I/O O Signal Level LVDS Description Divided Down Transmit Output Clock. This clock output is generated by dividing down the high-speed output clock, TXCLKOUT, to match the TXDOUT[15:0] word rate. This is accomplished by dividing by either 4 or 16, depending on the state of the MODE16 input. The TXCLK16OUT is provided for use in counter clocking schemes that transfer data between the system framer and the SI5100. (See REFSEL and REFRATE descriptions.) High-Speed Transmit Clock Disable. When this input is high, the output driver for TXCLKOUT is disabled. In applications that do not require the output data clock, the output clock driver should be disabled to save power. Note: This input has an internal pulldown. K12 TXCLKDSBL I LVTTL G1 H1 TXCLKOUT+ TXCLKOUT- O CML High-Speed Transmit Clock Output. The high-speed output clock, TXCLKOUT, is generated by the PLL in the clock multiplier unit. Its frequency is nominally 16 or 32 times the selected reference source. 32 Rev. 1.1 SI5100 Pin Number(s) J13 K13 J14 K14 L13 M13 L14 M14 N14 N13 P14 P13 N12 N11 P12 P11 N10 N9 P10 P9 N8 N7 P8 P7 N6 N5 P6 P5 N4 N3 P4 P3 K1 L1 Name TXDIN15+ TXDIN15- TXDIN14+ TXDIN14- TXDIN13+ TXDIN13- TXDIN12+ TXDIN12- TXDIN11+ TXDIN11- TXDIN10+ TXDIN10- TXDIN9+ TXDIN9- TXDIN8+ TXDIN8- TXDIN7+ TXDIN7- TXDIN6+ TXDIN6- TXDIN5+ TXDIN5- TXDIN4+ TXDIN4- TXDIN3+ TXDIN3- TXDIN2+ TXDIN2- TXDIN1+ TXDIN1- TXDIN0+ TXDIN0- TXDOUT+ TXDOUT- I/O I Signal Level LVDS Description Differential Parallel Transmit Data Input. The 4-bit or 16-bit data word present on these pins is multiplexed into a high-speed serial stream and output on TXDOUT. The data word size is set by the MODE16 input. The bit order for transmit multiplexing is selected by the TXMSBSEL input. The data on TXDIN[15:0] is clocked into the device by the rising edge of TXCLK16IN. O CML Differential High-Speed Transmit Data Output. The 4-bit or 16-bit word input on TXDIN[15:0] is multiplexed into a high-speed serial stream that is output on the TXDOUT pins. The data word size is set by the MODE16 input. The bit order for transmit multiplexing is selected by the TXMSBSEL input. The TXDOUT outputs are updated by the rising edge of TXCLKOUT. Transmit CMU Loss-of-Lock. The TXLOL output is asserted (low) when the CMU is not phase-locked to the selected reference source or if REFCLK is not present. See LOL in Table 5 on page 10. M5 TXLOL O LVTTL Rev. 1.1 33 SI5100 Pin Number(s) M9 Name TXMSBSEL I/O I Signal Level LVTTL Description Transmit Data Bus Bit Order Select. This input determines the order in which data bits received on the TXDIN[15:0] bus are transmitted on the high-speed serial output TXDOUT. For TXMSBSEL = 0, data on TXDIN0 is transmitted first followed by TXDIN1 through TXDIN15 (TXDIN1 through TXDOUT3 if MODE16 = 0). For TXMSBSEL = 1, TXDIN15 (TXDIN3) is transmitted first followed by TXDIN14 (TXDIN2) through TXDIN0. Note: This input has an internal pulldown. L3 TXREXT Transmitter External Bias Resistor. This resistor is used by the transmitter circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor. M12 TXSQLCH I LVTTL Transmit Data Squelch. When TXSQLCH is set low, the output data stream on TXDOUT is forced to a zero state. Set TXSQLCH high for normal operation. The TXSQLCH input is ignored when operating in line loopback mode (LLBK = 0). Note: This input has an internal pullup. E5-10, F5-10, G5-10, H5-10, J5-10, K5-10 H3 VDD VDDIO VDD VDDIO 1.8 V Supply Voltage. Nominally 1.8 V. C5 VREF O 1.8 V or 3.3 V LVTTL I/O Supply Voltage. Connect to either 1.8 or 3.3 V. When connected to 3.3 V, LVTTL compatible voltage swings are supported on the LVTTL inputs and LVTTL outputs of the device. Voltage Ref Voltage Reference. The SI5100 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k. The reference voltage is nominally 1.25 V. 34 Rev. 1.1 SI5100 18. Ordering Guide Part Number Package Temperature SI5100-F-BC 195-BGA -20 to 85 C Rev. 1.1 35 SI5100 19. Package Outline Figure 15 illustrates the package details for the SI5100. Table 9 lists the values for the dimensions shown in the illustration. P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 15. 195-Ball Grid Array (BGA) Table 9. Package Diagram Dimensions (mm) Dimension Description Min Millimeters Nom Max A A1 A2 b D D1 e L p S Total Package Height Standoff Body Thickness Solder Ball Diameter Body Size Total Array Pitch Solder Ball Pitch Die Size Die Offset Pitch to Centerline 2.75 0.65 1.30 0.65 2.90 0.70 1.40 0.70 15.00 BSC 13.00 BSC 1.00 BSC 3.05 0.75 1.50 0.75 3.10 3.18 2.53 BSC 0.50 BSC 3.25 36 Rev. 1.1 SI5100 20. 15x15 mm 195L CBGA Recommended PCB Layout Placement Courtyard Symbol Parameter Min Dimension Nom Max Notes C D E F X Column Width Row Height Pad Pitch Placement Courtyard Pad Diameter -- -- -- 16.00 0.64 13.00 REF 13.00 REF 1.00 BSC -- 0.68 -- -- -- -- 0.72 1 2, 3 Notes: 1. The Placement Courtyard is the minimum keep-out area required to assure assembly clearances. 2. Pad Diameter is Copper Defined (Non-Solder Mask Defined/NSMD). 3. OSP Surface Finish Recommended 4. Controlling dimension is millimeters. 5. Land Pad Dimensions comply with IPC-SM-782 guidelines. 6. Target solder paste volume per pad is 0.065 mm3 0.010 mm3 (4000 mils3 600 mils3). Recommended stencil aperture dimensions to achieve target solder paste volume are 0.191mm thick x 0.680.01 mm diameter, with a 0.025 mm taper. 7. Recommended stencil type is chemically etched stainless steel with circularly tapered apertures. Rev. 1.1 37 SI5100 DOCUMENT CHANGE LIST Revision 0.7 to Revision 1.0 Updated "SI5100 Detailed Block Diagram" on page 4 to clarify control of RXAMPMON and CMU timing source. Figure 1 on page 5 Clarified the measurement of VICM, VOCM and VI. Updated Table 3 on page 8. Updated Table 4 on page 9. Updated Table 5 on page 10. Updated Table 6 on page 11. Updated Table 7 on page 12. Updated dimension L in Table 9 on page 36. Updated "Functional Description" on page 14. Clarified frequency range, enabling RXAMPMON, and equations for VLOS. Updated "Clock and Data Recovery (CDR)" on page 15. Clarified slice and phase adjustment equations. Added Figure 4 on page 16. Corrected Figure 5 on page 17. Added Figure 11 on page 23. Added Figure 12 on page 23. Revision 1.0 to Revision 1.1 Updated Table 2 on page 6. Updated Figures 11 and 12 on page 23. Updated Table 9, "Package Diagram Dimensions (mm)," on page 36. 38 Rev. 1.1 SI5100 NOTES: Rev. 1.1 39 SI5100 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, SiPHY, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 40 Rev. 1.1 |
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